TABLE OF CONTENTS
Overview Block Diagram External Ports Processor processing_system7_0 Busses axi_interconnect_1 axi_interconnect_2 axi_interconnect_3 Peripherals axi_ad7780_0 axi_clkgen_0 axi_dma_0 axi_hdmi_tx_16b_0 axi_i2s_adi_0 axi_iic_0 axi_iic_1 axi_spdif_tx_0 axi_vdma_0 IP clock_generator_0 util_i2c_mixer_0 util_vector_logic_0 Timing Information

Overview | TOC Resources Used
1 | Processing System
3 | AXI Interconnect
1 | AXI Video DMA
1 | AXI_HDMI_TX_16B
1 | AXI_SPDIF_TX
2 | AXI IIC Interface
1 | AXI_CLKGEN
1 | Clock Generator
1 | Utility Vector Logic
1 | AXI_I2S_ADI
1 | UTIL_I2C_MIXER
1 | AXI DMA Engine
1 | axi_ad7780
| Specifics
Generated | Wed Sep 25 15:48:52 2013
EDK Version | 14.4
Device Family | zynq
Device | xc7z020clg484-1
Block Diagram | TOC
External Ports | TOC
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
SHARED | axi_i2s_adi_0_MCLK_pin | O | 1 | clock_generator_0_CLKOUT0 |
axi_ad7780_0 | axi_ad7780_0_dout_rdy_n_i_pin | I | 1 | axi_ad7780_0_dout_rdy_n_i |
axi_ad7780_0 | axi_ad7780_0_filter_o_pin | O | 1 | axi_ad7780_0_filter_o |
axi_ad7780_0 | axi_ad7780_0_gain_o_pin | O | 1 | axi_ad7780_0_gain_o |
axi_ad7780_0 | axi_ad7780_0_pdrst_o_pin | O | 1 | axi_ad7780_0_pdrst_o |
axi_ad7780_0 | axi_ad7780_0_sclk_o_pin | O | 1 | axi_ad7780_0_sclk_o | CLK
axi_hdmi_tx_16b_0 | hdmi_clk | O | 1 | axi_hdmi_tx_16b_0_hdmi_clk |
axi_hdmi_tx_16b_0 | hdmi_data | O | 0:15 | axi_hdmi_tx_16b_0_hdmi_data |
axi_hdmi_tx_16b_0 | hdmi_data_e | O | 1 | axi_hdmi_tx_16b_0_hdmi_data_e |
axi_hdmi_tx_16b_0 | hdmi_hsync | O | 1 | axi_hdmi_tx_16b_0_hdmi_hsync |
axi_hdmi_tx_16b_0 | hdmi_vsync | O | 1 | axi_hdmi_tx_16b_0_hdmi_vsync |
axi_i2s_adi_0 | axi_i2s_adi_0_SDATA_I_pin | I | 1 | axi_i2s_adi_0_SDATA_I |
axi_i2s_adi_0 | axi_i2s_adi_0_BCLK_O_pin | O | 1 | axi_i2s_adi_0_BCLK_O | CLK
axi_i2s_adi_0 | axi_i2s_adi_0_LRCLK_O_pin | O | 1 | axi_i2s_adi_0_LRCLK_O | CLK
axi_i2s_adi_0 | axi_i2s_adi_0_SDATA_O_pin | O | 1 | axi_i2s_adi_0_SDATA_O |
axi_iic_1 | axi_iic_1_Scl_pin | IO | 1 | axi_iic_1_Scl |
axi_iic_1 | axi_iic_1_Sda_pin | IO | 1 | axi_iic_1_Sda |
axi_spdif_tx_0 | hdmi_spdif | O | 1 | axi_spdif_tx_0_spdif_tx_o |
processing_system7_0 | processing_system7_0_PS_CLK | I | 1 | processing_system7_0_PS_CLK | CLK
processing_system7_0 | processing_system7_0_PS_PORB | I | 1 | processing_system7_0_PS_PORB |
processing_system7_0 | processing_system7_0_PS_SRSTB | I | 1 | processing_system7_0_PS_SRSTB |
processing_system7_0 | processing_system7_0_SPI0_MISO_I_pin | I | 1 | processing_system7_0_SPI0_MISO_I |
processing_system7_0 | processing_system7_0_SPI1_MISO_I_pin | I | 1 | processing_system7_0_SPI1_MISO_I |
processing_system7_0 | processing_system7_0_DDR_Addr | IO | 0:14 | processing_system7_0_DDR_Addr |
processing_system7_0 | processing_system7_0_DDR_BankAddr | IO | 0:2 | processing_system7_0_DDR_BankAddr |
processing_system7_0 | processing_system7_0_DDR_CAS_n | IO | 1 | processing_system7_0_DDR_CAS_n |
processing_system7_0 | processing_system7_0_DDR_CKE | IO | 1 | processing_system7_0_DDR_CKE |
processing_system7_0 | processing_system7_0_DDR_CS_n | IO | 1 | processing_system7_0_DDR_CS_n |
processing_system7_0 | processing_system7_0_DDR_Clk | IO | 1 | processing_system7_0_DDR_Clk | CLK
processing_system7_0 | processing_system7_0_DDR_Clk_n | IO | 1 | processing_system7_0_DDR_Clk_n | CLK
processing_system7_0 | processing_system7_0_DDR_DM | IO | 0:3 | processing_system7_0_DDR_DM |
processing_system7_0 | processing_system7_0_DDR_DQ | IO | 0:31 | processing_system7_0_DDR_DQ |
processing_system7_0 | processing_system7_0_DDR_DQS | IO | 0:3 | processing_system7_0_DDR_DQS |
processing_system7_0 | processing_system7_0_DDR_DQS_n | IO | 0:3 | processing_system7_0_DDR_DQS_n |
processing_system7_0 | processing_system7_0_DDR_DRSTB | IO | 1 | processing_system7_0_DDR_DRSTB | RESET
processing_system7_0 | processing_system7_0_DDR_ODT | IO | 1 | processing_system7_0_DDR_ODT |
processing_system7_0 | processing_system7_0_DDR_RAS_n | IO | 1 | processing_system7_0_DDR_RAS_n |
processing_system7_0 | processing_system7_0_DDR_VRN | IO | 1 | processing_system7_0_DDR_VRN |
processing_system7_0 | processing_system7_0_DDR_VRP | IO | 1 | processing_system7_0_DDR_VRP |
processing_system7_0 | processing_system7_0_GPIO_pin | IO | 0:30 | processing_system7_0_GPIO_0 |
processing_system7_0 | processing_system7_0_MIO | IO | 0:53 | processing_system7_0_MIO |
processing_system7_0 | otg_reset | O | 1 | net_vcc |
processing_system7_0 | processing_system7_0_DDR_WEB_pin | O | 1 | processing_system7_0_DDR_WEB |
processing_system7_0 | processing_system7_0_SPI0_MOSI_O_pin | O | 1 | processing_system7_0_SPI0_MOSI_O |
processing_system7_0 | processing_system7_0_SPI0_SCLK_O_pin | O | 1 | processing_system7_0_SPI0_SCLK_O | CLK
processing_system7_0 | processing_system7_0_SPI0_SS_O_pin | O | 1 | processing_system7_0_SPI0_SS_O |
processing_system7_0 | processing_system7_0_SPI1_MOSI_O_pin | O | 1 | processing_system7_0_SPI1_MOSI_O |
processing_system7_0 | processing_system7_0_SPI1_SCLK_O_pin | O | 1 | processing_system7_0_SPI1_SCLK_O | CLK
processing_system7_0 | processing_system7_0_SPI1_SS_O_pin | O | 1 | processing_system7_0_SPI1_SS_O |
util_i2c_mixer_0 | util_i2c_mixer_0_downstream_scl_pin | IO | 0:1 | util_i2c_mixer_0_downstream_scl |
util_i2c_mixer_0 | util_i2c_mixer_0_downstream_sda_pin | IO | 0:1 | util_i2c_mixer_0_downstream_sda |
util_vector_logic_0 | otg_vbusoc | I | 1 | net_otg_oc |
Unconnected | int_4_pin | I | 1 | int_4 | INTR
Unconnected | int_3_pin | I | 1 | int_3 | INTR
Unconnected | util_vector_logic_0_Op1_pin | I | 0:0 | net_util_vector_logic_0_Op1_pin |
Unconnected | int_2_pin | I | 1 | int_2 | INTR
Unconnected | hdmi_int | I | 1 | hdmi_int | INTR
Unconnected | int_1_pin | I | 1 | int_1 | INTR
Processors | TOC
processing_system7_0 Processing System Processing System wrapper for Series 7
IP Specs
Core | Version | Documentation
processing_system7 | 4.02.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MIO | IO | 1 | processing_system7_0_MIO
1 | PS_SRSTB | I | 1 | processing_system7_0_PS_SRSTB
2 | PS_CLK | I | 1 | processing_system7_0_PS_CLK
3 | PS_PORB | I | 1 | processing_system7_0_PS_PORB
4 | DDR_Clk | IO | 1 | processing_system7_0_DDR_Clk
5 | DDR_Clk_n | IO | 1 | processing_system7_0_DDR_Clk_n
6 | DDR_CKE | IO | 1 | processing_system7_0_DDR_CKE
7 | DDR_CS_n | IO | 1 | processing_system7_0_DDR_CS_n
8 | DDR_RAS_n | IO | 1 | processing_system7_0_DDR_RAS_n
9 | DDR_CAS_n | IO | 1 | processing_system7_0_DDR_CAS_n
10 | DDR_WEB | O | 1 | processing_system7_0_DDR_WEB
11 | DDR_BankAddr | IO | 1 | processing_system7_0_DDR_BankAddr
12 | DDR_Addr | IO | 1 | processing_system7_0_DDR_Addr
13 | DDR_ODT | IO | 1 | processing_system7_0_DDR_ODT
14 | DDR_DRSTB | IO | 1 | processing_system7_0_DDR_DRSTB
15 | DDR_DQ | IO | 1 | processing_system7_0_DDR_DQ
16 | DDR_DM | IO | 1 | processing_system7_0_DDR_DM
17 | DDR_DQS | IO | 1 | processing_system7_0_DDR_DQS
18 | DDR_DQS_n | IO | 1 | processing_system7_0_DDR_DQS_n
19 | DDR_VRN | IO | 1 | processing_system7_0_DDR_VRN
20 | DDR_VRP | IO | 1 | processing_system7_0_DDR_VRP
21 | FCLK_CLK0 | O | 1 | processing_system7_0_FCLK_CLK0
22 | FCLK_CLK1 | O | 1 | processing_system7_0_FCLK_CLK1
23 | FCLK_CLK2 | O | 1 | processing_system7_0_FCLK_CLK2
24 | FCLK_CLK3 | O | 1 | processing_system7_0_FCLK_CLK3
25 | FCLK_RESET0_N | O | 1 | processing_system7_0_FCLK_RESET0_N
26 | FCLK_RESET1_N | O | 1 | processing_system7_0_FCLK_RESET1_N
27 | M_AXI_GP0_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
28 | S_AXI_HP0_ACLK | I | 1 | processing_system7_0_FCLK_CLK1
29 | S_AXI_HP1_ACLK | I | 1 | processing_system7_0_FCLK_CLK1
30 | IRQ_F2P | I | 1 | axi_vdma_0_mm2s_introut & axi_iic_0_IIC2INTC_Irpt & axi_iic_1_IIC2INTC_Irpt & int_1 & int_2 & int_3 & int_4 & axi_dma_0_mm2s_introut & axi_dma_0_s2mm_introut
31 | USB0_VBUS_PWRFAULT | I | 1 | util_vector_logic_0_Res
32 | DMA0_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
33 | DMA0_RSTN | O | 1 | processing_system7_0_DMA0_RSTN
34 | DMA0_DATYPE | O | 1 | processing_system7_0_DMA0_DATYPE
35 | DMA0_DAVALID | O | 1 | processing_system7_0_DMA0_DAVALID
36 | DMA0_DRREADY | O | 1 | processing_system7_0_DMA0_DRREADY
37 | DMA0_DAREADY | I | 1 | axi_spdif_tx_0_DMA_REQ_DAREADY
38 | DMA0_DRLAST | I | 1 | axi_spdif_tx_0_DMA_REQ_DRLAST
39 | DMA0_DRTYPE | I | 1 | axi_spdif_tx_0_DMA_REQ_DRTYPE
40 | DMA0_DRVALID | I | 1 | axi_spdif_tx_0_DMA_REQ_DRVALID
41 | DMA1_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
42 | DMA1_DAVALID | O | 1 | processing_system7_0_DMA1_DAVALID
43 | DMA1_DATYPE | O | 1 | processing_system7_0_DMA1_DATYPE
44 | DMA1_DRREADY | O | 1 | processing_system7_0_DMA1_DRREADY
45 | DMA1_RSTN | O | 1 | processing_system7_0_DMA1_RSTN
46 | DMA1_DRVALID | I | 1 | axi_i2s_adi_0_DMA_REQ_TX_DRVALID
47 | DMA1_DRTYPE | I | 1 | axi_i2s_adi_0_DMA_REQ_TX_DRTYPE
48 | DMA1_DAREADY | I | 1 | axi_i2s_adi_0_DMA_REQ_TX_DAREADY
49 | DMA1_DRLAST | I | 1 | axi_i2s_adi_0_DMA_REQ_TX_DRLAST
50 | DMA2_DATYPE | O | 1 | processing_system7_0_DMA2_DATYPE
51 | DMA2_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
52 | DMA2_DAVALID | O | 1 | processing_system7_0_DMA2_DAVALID
53 | DMA2_DRREADY | O | 1 | processing_system7_0_DMA2_DRREADY
54 | DMA2_RSTN | O | 1 | processing_system7_0_DMA2_RSTN
55 | DMA2_DRLAST | I | 1 | axi_i2s_adi_0_DMA_REQ_RX_DRLAST
56 | DMA2_DRVALID | I | 1 | axi_i2s_adi_0_DMA_REQ_RX_DRVALID
57 | DMA2_DRTYPE | I | 1 | axi_i2s_adi_0_DMA_REQ_RX_DRTYPE
58 | DMA2_DAREADY | I | 1 | axi_i2s_adi_0_DMA_REQ_RX_DAREADY
59 | GPIO | IO | 1 | processing_system7_0_GPIO_0
60 | SPI0_SCLK_O | O | 1 | processing_system7_0_SPI0_SCLK_O
61 | SPI0_MOSI_O | O | 1 | processing_system7_0_SPI0_MOSI_O
62 | SPI0_MISO_I | I | 1 | processing_system7_0_SPI0_MISO_I
63 | SPI0_SS_O | O | 1 | processing_system7_0_SPI0_SS_O
64 | SPI0_SS_I | I | 1 | net_vcc
65 | SPI1_SCLK_O | O | 1 | processing_system7_0_SPI1_SCLK_O
66 | SPI1_MOSI_O | O | 1 | processing_system7_0_SPI1_MOSI_O
67 | SPI1_MISO_I | I | 1 | processing_system7_0_SPI1_MISO_I
68 | SPI1_SS_O | O | 1 | processing_system7_0_SPI1_SS_O
69 | SPI1_SS_I | I | 1 | net_vcc
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
M_AXI_GP0 | MASTER | AXI | axi_interconnect_1 | 9 Peripherals.
S_AXI_HP0 | SLAVE | AXI | axi_interconnect_2 | axi_vdma_0
S_AXI_HP1 | SLAVE | AXI | axi_interconnect_3 | axi_dma_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EN_EMIO_CAN0 | 0
C_EN_EMIO_CAN1 | 0
C_EN_EMIO_ENET0 | 0
C_EN_EMIO_ENET1 | 0
C_EN_EMIO_GPIO | 1
C_EN_EMIO_I2C0 | 0
C_EN_EMIO_I2C1 | 0
C_EN_EMIO_PJTAG | 0
C_EN_EMIO_SDIO0 | 0
C_EN_EMIO_CD_SDIO0 | 0
C_EN_EMIO_WP_SDIO0 | 0
C_EN_EMIO_SDIO1 | 0
C_EN_EMIO_CD_SDIO1 | 0
C_EN_EMIO_WP_SDIO1 | 0
C_EN_EMIO_SPI0 | 1
C_EN_EMIO_SPI1 | 1
C_EN_EMIO_UART0 | 0
C_EN_EMIO_UART1 | 0
C_EN_EMIO_MODEM_UART0 | 0
C_EN_EMIO_MODEM_UART1 | 0
C_EN_EMIO_TTC0 | 0
C_EN_EMIO_TTC1 | 0
C_EN_EMIO_WDT | 0
C_EN_EMIO_TRACE | 0
C_USE_M_AXI_GP0 | 1
C_USE_M_AXI_GP1 | 0
C_USE_S_AXI_GP0 | 0
C_USE_S_AXI_GP1 | 0
C_USE_S_AXI_ACP | 0
C_USE_S_AXI_HP0 | 1
C_USE_S_AXI_HP1 | 1
C_USE_S_AXI_HP2 | 0
C_USE_S_AXI_HP3 | 0
C_S_AXI_GP0_ENABLE_LOWOCM_DDR | 0
C_S_AXI_GP1_ENABLE_LOWOCM_DDR | 0
C_S_AXI_ACP_ENABLE_HIGHOCM | 0
C_S_AXI_HP0_ENABLE_HIGHOCM | 0
C_S_AXI_HP1_ENABLE_HIGHOCM | 0
C_S_AXI_HP2_ENABLE_HIGHOCM | 0
C_S_AXI_HP3_ENABLE_HIGHOCM | 0
C_USE_DMA0 | 1
C_USE_DMA1 | 1
C_USE_DMA2 | 1
C_USE_DMA3 | 0
C_USE_TRACE | 0
C_INCLUDE_TRACE_BUFFER | 0
C_TRACE_BUFFER_FIFO_SIZE | 128
USE_TRACE_DATA_EDGE_DETECTOR | 0
C_TRACE_BUFFER_CLOCK_DELAY | 12
C_USE_CROSS_TRIGGER | 0
C_USE_CR_FABRIC | 1
C_USE_AXI_FABRIC_IDLE | 0
C_USE_DDR_BYPASS | 0
C_USE_FABRIC_INTERRUPT | 1
C_USE_PROC_EVENT_BUS | 0
C_EN_EMIO_SRAM_INT | 0
C_EMIO_GPIO_WIDTH | 31
C_INCLUDE_ACP_TRANS_CHECK | 0
C_USE_DEFAULT_ACP_USER_VAL | 0
C_S_AXI_ACP_ARUSER_VAL | 31
C_S_AXI_ACP_AWUSER_VAL | 31
C_DQ_WIDTH | 32
C_DQS_WIDTH | 4
C_DM_WIDTH | 4
C_MIO_PRIMITIVE | 54
C_PACKAGE_NAME | clg484
C_PS7_SI_REV | PRODUCTION
C_UART_BAUD_RATE | 115200
C_DDR_RAM_BASEADDR | 0x00000000
C_DDR_RAM_HIGHADDR | 0x1FFFFFFF
C_UART0_BASEADDR | 0xE0000000
C_UART0_HIGHADDR | 0xE0000FFF
C_UART1_BASEADDR | 0xE0001000
C_UART1_HIGHADDR | 0xE0001FFF
C_I2C0_BASEADDR | 0xE0004000
C_I2C0_HIGHADDR | 0xE0004FFF
C_I2C1_BASEADDR | 0xE0005000
C_I2C1_HIGHADDR | 0xE0005FFF
C_SPI0_BASEADDR | 0xE0006000
C_SPI0_HIGHADDR | 0xE0006FFF
C_SPI1_BASEADDR | 0xE0007000
C_SPI1_HIGHADDR | 0xE0007FFF
C_CAN0_BASEADDR | 0xE0008000
C_CAN0_HIGHADDR | 0xE0008FFF
C_CAN1_BASEADDR | 0xE0009000
C_CAN1_HIGHADDR | 0xE0009FFF
C_GPIO_BASEADDR | 0xE000A000
C_GPIO_HIGHADDR | 0xE000AFFF
C_ENET0_BASEADDR | 0xE000B000
C_ENET0_HIGHADDR | 0xE000BFFF
C_ENET1_BASEADDR | 0xE000C000
C_ENET1_HIGHADDR | 0xE000CFFF
C_SDIO0_BASEADDR | 0xE0100000
C_SDIO0_HIGHADDR | 0xE0100FFF
C_SDIO1_BASEADDR | 0xE0101000
C_SDIO1_HIGHADDR | 0xE0101FFF
C_USB0_BASEADDR | 0xE0102000
C_USB0_HIGHADDR | 0xE0102FFF
C_USB1_BASEADDR | 0xE0103000
C_USB1_HIGHADDR | 0xE0103FFF
C_TTC0_BASEADDR | 0xE0104000
C_TTC0_HIGHADDR | 0xE0104FFF
C_TTC1_BASEADDR | 0xE0105000
C_TTC1_HIGHADDR | 0xE0105FFF
C_M_AXI_GP0_PROTOCOL | AXI3
C_M_AXI_GP0_ID_WIDTH | 12
C_M_AXI_GP0_ADDR_WIDTH | 32
C_M_AXI_GP0_DATA_WIDTH | 32
C_M_AXI_GP0_ENABLE_STATIC_REMAP | 0
C_M_AXI_GP0_SUPPORTS_NARROW_BURST | 0
C_M_AXI_GP0_SUPPORTS_REORDERING | 0
C_INTERCONNECT_M_AXI_GP0_WRITE_ISSUING | 8
C_INTERCONNECT_M_AXI_GP0_READ_ISSUING | 8
C_M_AXI_GP1_PROTOCOL | AXI3
C_M_AXI_GP1_ID_WIDTH | 12
C_M_AXI_GP1_ADDR_WIDTH | 32
C_M_AXI_GP1_DATA_WIDTH | 32
C_M_AXI_GP1_ENABLE_STATIC_REMAP | 0
C_M_AXI_GP1_SUPPORTS_NARROW_BURST | 0 |  | Name | Value
C_M_AXI_GP1_SUPPORTS_REORDERING | 0
C_INTERCONNECT_M_AXI_GP1_WRITE_ISSUING | 8
C_INTERCONNECT_M_AXI_GP1_READ_ISSUING | 8
C_S_AXI_GP0_PROTOCOL | AXI3
C_S_AXI_GP0_ID_WIDTH | 6
C_S_AXI_GP0_ADDR_WIDTH | 32
C_S_AXI_GP0_DATA_WIDTH | 32
C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE | 8
C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE | 8
C_S_AXI_GP1_PROTOCOL | AXI3
C_S_AXI_GP1_ID_WIDTH | 6
C_S_AXI_GP1_ADDR_WIDTH | 32
C_S_AXI_GP1_DATA_WIDTH | 32
C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE | 8
C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE | 8
C_S_AXI_ACP_PROTOCOL | AXI3
C_S_AXI_ACP_ID_WIDTH | 3
C_S_AXI_ACP_ADDR_WIDTH | 32
C_S_AXI_ACP_DATA_WIDTH | 64
C_S_AXI_ACP_SUPPORTS_USER_SIGNALS | 1
C_S_AXI_ACP_ARUSER_WIDTH | 5
C_S_AXI_ACP_AWUSER_WIDTH | 5
C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE | 8
C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE | 8
C_S_AXI_HP0_PROTOCOL | AXI3
C_S_AXI_HP0_ID_WIDTH | 6
C_S_AXI_HP0_ADDR_WIDTH | 32
C_S_AXI_HP0_DATA_WIDTH | 64
C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE | 8
C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE | 8
C_S_AXI_HP1_PROTOCOL | AXI3
C_S_AXI_HP1_ID_WIDTH | 6
C_S_AXI_HP1_ADDR_WIDTH | 32
C_S_AXI_HP1_DATA_WIDTH | 64
C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE | 8
C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE | 8
C_S_AXI_HP2_PROTOCOL | AXI3
C_S_AXI_HP2_ID_WIDTH | 6
C_S_AXI_HP2_ADDR_WIDTH | 32
C_S_AXI_HP2_DATA_WIDTH | 64
C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE | 8
C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE | 8
C_S_AXI_HP3_PROTOCOL | AXI3
C_S_AXI_HP3_ID_WIDTH | 6
C_S_AXI_HP3_ADDR_WIDTH | 32
C_S_AXI_HP3_DATA_WIDTH | 64
C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE | 8
C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE | 8
C_S_AXI_GP0_BASEADDR | 0xE0000000
C_S_AXI_GP0_HIGHADDR | 0xFFFFFFFF
C_S_AXI_GP0_LOWOCM_DDR_BASEADDR | 0x00000000
C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR | 0x3FFFFFFF
C_S_AXI_GP1_BASEADDR | 0xE0000000
C_S_AXI_GP1_HIGHADDR | 0xFFFFFFFF
C_S_AXI_GP1_LOWOCM_DDR_BASEADDR | 0x00000000
C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR | 0x3FFFFFFF
C_S_AXI_ACP_BASEADDR | 0x00000000
C_S_AXI_ACP_HIGHADDR | 0x3FFFFFFF
C_S_AXI_ACP_HIGHOCM_BASEADDR | 0xFFFC0000
C_S_AXI_ACP_HIGHOCM_HIGHADDR | 0xFFFFFFFF
C_S_AXI_HP0_BASEADDR | 0x00000000
C_S_AXI_HP0_HIGHADDR | 0x3FFFFFFF
C_S_AXI_HP0_HIGHOCM_BASEADDR | 0xFFFC0000
C_S_AXI_HP0_HIGHOCM_HIGHADDR | 0xFFFFFFFF
C_S_AXI_HP1_BASEADDR | 0x00000000
C_S_AXI_HP1_HIGHADDR | 0x3FFFFFFF
C_S_AXI_HP1_HIGHOCM_BASEADDR | 0xFFFC0000
C_S_AXI_HP1_HIGHOCM_HIGHADDR | 0xFFFFFFFF
C_S_AXI_HP2_BASEADDR | 0x00000000
C_S_AXI_HP2_HIGHADDR | 0x3FFFFFFF
C_S_AXI_HP2_HIGHOCM_BASEADDR | 0xFFFC0000
C_S_AXI_HP2_HIGHOCM_HIGHADDR | 0xFFFFFFFF
C_S_AXI_HP3_BASEADDR | 0x00000000
C_S_AXI_HP3_HIGHADDR | 0x3FFFFFFF
C_S_AXI_HP3_HIGHOCM_BASEADDR | 0xFFFC0000
C_S_AXI_HP3_HIGHOCM_HIGHADDR | 0xFFFFFFFF
C_M_AXI_GP0_SUPPORTS_THREADS | 1
C_M_AXI_GP0_THREAD_ID_WIDTH | 12
C_M_AXI_GP1_SUPPORTS_THREADS | 1
C_M_AXI_GP1_THREAD_ID_WIDTH | 12
C_NUM_F2P_INTR_INPUTS | 9
C_EN_DDR | 1
C_EN_SMC | 0
C_EN_QSPI | 1
C_EN_CAN0 | 0
C_EN_CAN1 | 0
C_EN_ENET0 | 1
C_EN_ENET1 | 0
C_EN_GPIO | 1
C_EN_I2C0 | 0
C_EN_I2C1 | 0
C_EN_PJTAG | 0
C_EN_SDIO0 | 1
C_EN_SDIO1 | 0
C_EN_SPI0 | 1
C_EN_SPI1 | 1
C_EN_UART0 | 0
C_EN_UART1 | 1
C_EN_MODEM_UART0 | 0
C_EN_MODEM_UART1 | 0
C_EN_TTC0 | 0
C_EN_TTC1 | 0
C_EN_WDT | 0
C_EN_TRACE | 0
C_EN_USB0 | 1
C_EN_USB1 | 0
C_EN_4K_TIMER | 0
C_FCLK_CLK0_FREQ | 100000000
C_FCLK_CLK1_FREQ | 142857132
C_FCLK_CLK2_FREQ | 200000000
C_FCLK_CLK3_FREQ | 20000000
C_FCLK_CLK0_BUF | TRUE
C_FCLK_CLK1_BUF | TRUE
C_FCLK_CLK2_BUF | TRUE
C_FCLK_CLK3_BUF | TRUE
C_INTERCONNECT_S_AXI_HP0_MASTERS | axi_vdma_0.M_AXI_MM2S
C_INTERCONNECT_S_AXI_HP1_MASTERS | axi_dma_0.M_AXI_S2MM
C_INTERCONNECT_S_AXI_HP2_MASTERS | axi_dma_i2s.M_AXI_MM2S & axi_dma_i2s.M_AXI_SG & axi_dma_i2s.M_AXI_S2MM
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Busses | TOC
axi_interconnect_1 AXI Interconnect AXI4 Memory-Mapped Interconnect
IP Specs
Core | Version | Documentation
axi_interconnect | 1.06.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | INTERCONNECT_ARESETN | I | 1 | processing_system7_0_FCLK_RESET0_N
1 | INTERCONNECT_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
processing_system7_0 | MASTER | M_AXI_GP0
axi_vdma_0 | SLAVE | S_AXI_LITE
axi_hdmi_tx_16b_0 | SLAVE | S_AXI
axi_spdif_tx_0 | SLAVE | S_AXI
axi_iic_0 | SLAVE | S_AXI
axi_clkgen_0 | SLAVE | S_AXI
axi_i2s_adi_0 | SLAVE | S_AXI
axi_iic_1 | SLAVE | S_AXI
axi_dma_0 | SLAVE | S_AXI_LITE
axi_ad7780_0 | SLAVE | S_AXI
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | rtl
C_BASEFAMILY | rtl
C_NUM_SLAVE_SLOTS | 1
C_NUM_MASTER_SLOTS | 1
C_AXI_ID_WIDTH | 1
C_AXI_ADDR_WIDTH | 32
C_AXI_DATA_MAX_WIDTH | 32
C_S_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR |
C_M_AXI_HIGH_ADDR |
C_S_AXI_BASE_ID | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT | 0b0000000000000000
C_S_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_M_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO | 1
C_S_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_S_AXI_SUPPORTS_READ | 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_M_AXI_SUPPORTS_READ | 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS | 0
C_AXI_AWUSER_WIDTH | 1
C_AXI_ARUSER_WIDTH | 1
C_AXI_WUSER_WIDTH | 1
C_AXI_RUSER_WIDTH | 1
C_AXI_BUSER_WIDTH | 1
C_AXI_CONNECTIVITY | 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD | 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING | 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 |  | Name | Value
C_M_AXI_READ_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE | 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_S_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER | 0
C_INTERCONNECT_CONNECTIVITY_MODE | 0
C_USE_CTRL_PORT | 0
C_USE_INTERRUPT | 1
C_RANGE_CHECK | 2
C_S_AXI_CTRL_PROTOCOL | AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_BASEADDR | 0xFFFFFFFF
C_HIGHADDR | 0x00000000
C_DEBUG | 0
C_S_AXI_DEBUG_SLOT | 0
C_M_AXI_DEBUG_SLOT | 0
C_MAX_DEBUG_THREADS | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_interconnect_2 AXI Interconnect AXI4 Memory-Mapped Interconnect
IP Specs
Core | Version | Documentation
axi_interconnect | 1.06.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | INTERCONNECT_ACLK | I | 1 | processing_system7_0_FCLK_CLK1
1 | INTERCONNECT_ARESETN | I | 1 | processing_system7_0_FCLK_RESET1_N
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
axi_vdma_0 | MASTER | M_AXI_MM2S
processing_system7_0 | SLAVE | S_AXI_HP0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | rtl
C_BASEFAMILY | rtl
C_NUM_SLAVE_SLOTS | 1
C_NUM_MASTER_SLOTS | 1
C_AXI_ID_WIDTH | 1
C_AXI_ADDR_WIDTH | 32
C_AXI_DATA_MAX_WIDTH | 32
C_S_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR |
C_M_AXI_HIGH_ADDR |
C_S_AXI_BASE_ID | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT | 0b0000000000000000
C_S_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_M_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO | 1
C_S_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_S_AXI_SUPPORTS_READ | 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_M_AXI_SUPPORTS_READ | 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS | 0
C_AXI_AWUSER_WIDTH | 1
C_AXI_ARUSER_WIDTH | 1
C_AXI_WUSER_WIDTH | 1
C_AXI_RUSER_WIDTH | 1
C_AXI_BUSER_WIDTH | 1
C_AXI_CONNECTIVITY | 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD | 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING | 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 |  | Name | Value
C_M_AXI_READ_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE | 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_S_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER | 0
C_INTERCONNECT_CONNECTIVITY_MODE | 1
C_USE_CTRL_PORT | 0
C_USE_INTERRUPT | 1
C_RANGE_CHECK | 2
C_S_AXI_CTRL_PROTOCOL | AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_BASEADDR | 0xFFFFFFFF
C_HIGHADDR | 0x00000000
C_DEBUG | 0
C_S_AXI_DEBUG_SLOT | 0
C_M_AXI_DEBUG_SLOT | 0
C_MAX_DEBUG_THREADS | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_interconnect_3 AXI Interconnect AXI4 Memory-Mapped Interconnect
IP Specs
Core | Version | Documentation
axi_interconnect | 1.06.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | INTERCONNECT_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
1 | INTERCONNECT_ARESETN | I | 1 | processing_system7_0_FCLK_RESET1_N
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
axi_dma_0 | MASTER | M_AXI_S2MM
processing_system7_0 | SLAVE | S_AXI_HP1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | rtl
C_BASEFAMILY | rtl
C_NUM_SLAVE_SLOTS | 1
C_NUM_MASTER_SLOTS | 1
C_AXI_ID_WIDTH | 1
C_AXI_ADDR_WIDTH | 32
C_AXI_DATA_MAX_WIDTH | 32
C_S_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR |
C_M_AXI_HIGH_ADDR |
C_S_AXI_BASE_ID | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT | 0b0000000000000000
C_S_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_M_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO | 1
C_S_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_S_AXI_SUPPORTS_READ | 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_M_AXI_SUPPORTS_READ | 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS | 0
C_AXI_AWUSER_WIDTH | 1
C_AXI_ARUSER_WIDTH | 1
C_AXI_WUSER_WIDTH | 1
C_AXI_RUSER_WIDTH | 1
C_AXI_BUSER_WIDTH | 1
C_AXI_CONNECTIVITY | 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD | 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING | 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 |  | Name | Value
C_M_AXI_READ_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE | 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_S_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER | 0
C_INTERCONNECT_CONNECTIVITY_MODE | 1
C_USE_CTRL_PORT | 0
C_USE_INTERRUPT | 1
C_RANGE_CHECK | 2
C_S_AXI_CTRL_PROTOCOL | AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_BASEADDR | 0xFFFFFFFF
C_HIGHADDR | 0x00000000
C_DEBUG | 0
C_S_AXI_DEBUG_SLOT | 0
C_M_AXI_DEBUG_SLOT | 0
C_MAX_DEBUG_THREADS | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Peripherals | TOC
axi_ad7780_0 axi_ad7780
IP Specs
Core | Version
axi_ad7780 | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | s_axi_aclk | I | 1 | processing_system7_0_FCLK_CLK0
1 | dout_rdy_n_i | I | 1 | axi_ad7780_0_dout_rdy_n_i
2 | filter_o | O | 1 | axi_ad7780_0_filter_o
3 | gain_o | O | 1 | axi_ad7780_0_gain_o
4 | pdrst_o | O | 1 | axi_ad7780_0_pdrst_o
5 | sclk_o | O | 1 | axi_ad7780_0_sclk_o
6 | ref_clk | I | 1 | processing_system7_0_FCLK_CLK0
7 | rx_clk | I | 1 | processing_system7_0_FCLK_CLK3
8 | s_axis_s2mm_clk | I | 1 | processing_system7_0_FCLK_CLK0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXIS_S2MM | INITIATOR | AXIS | axi_ad7780_0_S_AXIS_S2MM | axi_dma_0
S_AXI | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
PCORE_ID | 0
PCORE_DEVICE_TYPE | 0
PCORE_IODELAY_GROUP | adc_if_delay_group
C_S_AXI_MIN_SIZE | 0x0000FFFF
C_BASEADDR | 0x79020000
C_HIGHADDR | 0x7902FFFF
C_S_AXI_PROTOCOL | AXI4LITE
C_S_AXIS_S2MM_PROTOCOL | XIL_AXI_STREAM_ETH_DATA Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_clkgen_0 AXI_CLKGEN
IP Specs
Core | Version
axi_clkgen | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
1 | ref_clk | I | 1 | processing_system7_0_FCLK_CLK2
2 | clk | O | 1 | axi_hdmi_tx_16b_0_hdmi_ref_clk
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_MIN_SIZE | 0x000001FF
C_USE_WSTRB | 0
C_DPHASE_TIMEOUT | 8
C_BASEADDR | 0x79000000
C_HIGHADDR | 0x7900FFFF |  | Name | Value
C_FAMILY | virtex6
C_NUM_REG | 1
C_NUM_MEM | 1
C_SLV_AWIDTH | 32
C_SLV_DWIDTH | 32
C_S_AXI_PROTOCOL | AXI4LITE
C_MMCM_TYPE | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_dma_0 AXI DMA Engine AXI MemoryMap to/from AXI Stream Direct Memory Access Engine
IP Specs
Core | Version | Documentation
axi_dma | 6.03.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | m_axi_sg_aclk | I | 1 | processing_system7_0_FCLK_CLK0
1 | m_axi_mm2s_aclk | I | 1 | processing_system7_0_FCLK_CLK0
2 | m_axi_s2mm_aclk | I | 1 | processing_system7_0_FCLK_CLK0
3 | s_axi_lite_aclk | I | 1 | processing_system7_0_FCLK_CLK0
4 | mm2s_introut | O | 1 | axi_dma_0_mm2s_introut
5 | s2mm_introut | O | 1 | axi_dma_0_s2mm_introut
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
M_AXI_S2MM | MASTER | AXI | axi_interconnect_3 | processing_system7_0
S_AXI_LITE | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
S_AXIS_S2MM | TARGET | AXIS | axi_ad7780_0_S_AXIS_S2MM | axi_ad7780_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_M_AXI_SG_AWUSER_WIDTH | 4
C_M_AXI_SG_ARUSER_WIDTH | 4
C_M_AXI_MM2S_ARUSER_WIDTH | 4
C_M_AXI_S2MM_AWUSER_WIDTH | 4
C_S_AXI_LITE_ADDR_WIDTH | 10
C_S_AXI_LITE_DATA_WIDTH | 32
C_DLYTMR_RESOLUTION | 125
C_PRMRY_IS_ACLK_ASYNC | 0
C_INCLUDE_SG | 0
C_ENABLE_MULTI_CHANNEL | 0
C_SG_INCLUDE_DESC_QUEUE | 0
C_SG_INCLUDE_STSCNTRL_STRM | 1
C_SG_USE_STSAPP_LENGTH | 1
C_SG_LENGTH_WIDTH | 23
C_M_AXI_SG_ADDR_WIDTH | 32
C_M_AXI_SG_DATA_WIDTH | 32
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH | 32
C_S_AXIS_S2MM_STS_TDATA_WIDTH | 32
C_INCLUDE_MM2S | 0
C_INCLUDE_MM2S_SF | 1
C_INCLUDE_MM2S_DRE | 0
C_MM2S_BURST_SIZE | 16
C_M_AXI_MM2S_ADDR_WIDTH | 32
C_M_AXI_MM2S_DATA_WIDTH | 32
C_M_AXIS_MM2S_TDATA_WIDTH | 32
C_INCLUDE_S2MM | 1
C_INCLUDE_S2MM_SF | 1
C_INCLUDE_S2MM_DRE | 0
C_S2MM_BURST_SIZE | 256
C_M_AXI_S2MM_ADDR_WIDTH | 32
C_M_AXI_S2MM_DATA_WIDTH | 32
C_S_AXIS_S2MM_TDATA_WIDTH | 32
C_NUM_S2MM_CHANNELS | 1
C_NUM_MM2S_CHANNELS | 1 |  | Name | Value
C_FAMILY | virtex6
C_INSTANCE | axi_dma
C_BASEADDR | 0x40400000
C_HIGHADDR | 0x4040FFFF
C_S_AXI_LITE_PROTOCOL | AXI4LITE
C_S_AXI_LITE_SUPPORTS_READ | 1
C_S_AXI_LITE_SUPPORTS_WRITE | 1
C_M_AXI_SG_PROTOCOL | AXI4
C_M_AXI_SG_SUPPORTS_THREADS | 0
C_M_AXI_SG_THREAD_ID_WIDTH | 1
C_M_AXI_SG_SUPPORTS_NARROW_BURST | 0
C_M_AXI_SG_SUPPORTS_READ | 1
C_M_AXI_SG_SUPPORTS_WRITE | 1
C_M_AXI_MM2S_PROTOCOL | AXI4
C_M_AXI_MM2S_SUPPORTS_THREADS | 0
C_M_AXI_MM2S_THREAD_ID_WIDTH | 1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST | 0
C_M_AXI_MM2S_SUPPORTS_READ | 1
C_M_AXI_MM2S_SUPPORTS_WRITE | 0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING | 4
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH | 512
C_M_AXI_S2MM_PROTOCOL | AXI4
C_M_AXI_S2MM_SUPPORTS_THREADS | 0
C_M_AXI_S2MM_THREAD_ID_WIDTH | 1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST | 0
C_M_AXI_S2MM_SUPPORTS_WRITE | 1
C_M_AXI_S2MM_SUPPORTS_READ | 0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING | 4
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH | 512
C_M_AXIS_MM2S_CNTRL_PROTOCOL | XIL_AXI_STREAM_ETH_CTRL
C_S_AXIS_S2MM_STS_PROTOCOL | XIL_AXI_STREAM_ETH_CTRL
C_M_AXIS_MM2S_PROTOCOL | XIL_AXI_STREAM_ETH_DATA
C_S_AXIS_S2MM_PROTOCOL | XIL_AXI_STREAM_ETH_DATA
C_GENERIC | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_hdmi_tx_16b_0 AXI_HDMI_TX_16B
IP Specs
Core | Version
axi_hdmi_tx_16b | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
1 | hdmi_ref_clk | I | 1 | axi_hdmi_tx_16b_0_hdmi_ref_clk
2 | hdmi_clk | O | 1 | axi_hdmi_tx_16b_0_hdmi_clk
3 | hdmi_data | O | 1 | axi_hdmi_tx_16b_0_hdmi_data
4 | hdmi_hsync | O | 1 | axi_hdmi_tx_16b_0_hdmi_hsync
5 | hdmi_vsync | O | 1 | axi_hdmi_tx_16b_0_hdmi_vsync
6 | hdmi_data_e | O | 1 | axi_hdmi_tx_16b_0_hdmi_data_e
7 | vdma_clk | I | 1 | processing_system7_0_FCLK_CLK1
8 | vdma_fs | O | 1 | axi_hdmi_tx_16b_0_vdma_fs
9 | vdma_fs_ret | I | 1 | axi_vdma_0_mm2s_fsync_out
10 | vdma_empty | I | 1 | axi_vdma_0_mm2s_buffer_empty
11 | vdma_almost_empty | I | 1 | axi_vdma_0_mm2s_buffer_almost_empty
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
M_AXIS_MM2S | TARGET | AXIS | axi_vdma_0_M_AXIS_MM2S | axi_vdma_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_MIN_SIZE | 0x000001FF
C_USE_WSTRB | 0
C_DPHASE_TIMEOUT | 8
C_BASEADDR | 0x70E00000
C_HIGHADDR | 0x70E0FFFF |  | Name | Value
C_FAMILY | virtex6
C_NUM_REG | 1
C_NUM_MEM | 1
C_SLV_AWIDTH | 32
C_SLV_DWIDTH | 32
C_S_AXI_PROTOCOL | AXI4LITE
C_M_AXIS_MM2S_PROTOCOL | XIL_AXI_STREAM_VID_DATA Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_i2s_adi_0 AXI_I2S_ADI
IP Specs
Core | Version
axi_i2s_adi | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | DATA_CLK_I | I | 1 | clock_generator_0_CLKOUT0
1 | BCLK_O | O | 1 | axi_i2s_adi_0_BCLK_O
2 | LRCLK_O | O | 1 | axi_i2s_adi_0_LRCLK_O
3 | SDATA_I | I | 1 | axi_i2s_adi_0_SDATA_I
4 | SDATA_O | O | 1 | axi_i2s_adi_0_SDATA_O
5 | S_AXI_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
6 | DMA_REQ_RX_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
7 | DMA_REQ_TX_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
8 | DMA_REQ_TX_DAVALID | I | 1 | processing_system7_0_DMA1_DAVALID
9 | DMA_REQ_TX_DATYPE | I | 1 | processing_system7_0_DMA1_DATYPE
10 | DMA_REQ_TX_DRREADY | I | 1 | processing_system7_0_DMA1_DRREADY
11 | DMA_REQ_TX_RSTN | I | 1 | processing_system7_0_DMA1_RSTN
12 | DMA_REQ_TX_DRVALID | O | 1 | axi_i2s_adi_0_DMA_REQ_TX_DRVALID
13 | DMA_REQ_TX_DRTYPE | O | 1 | axi_i2s_adi_0_DMA_REQ_TX_DRTYPE
14 | DMA_REQ_TX_DRLAST | O | 1 | axi_i2s_adi_0_DMA_REQ_TX_DRLAST
15 | DMA_REQ_TX_DAREADY | O | 1 | axi_i2s_adi_0_DMA_REQ_TX_DAREADY
16 | DMA_REQ_RX_DATYPE | I | 1 | processing_system7_0_DMA2_DATYPE
17 | DMA_REQ_RX_DAVALID | I | 1 | processing_system7_0_DMA2_DAVALID
18 | DMA_REQ_RX_DRREADY | I | 1 | processing_system7_0_DMA2_DRREADY
19 | DMA_REQ_RX_RSTN | I | 1 | processing_system7_0_DMA2_RSTN
20 | DMA_REQ_RX_DRLAST | O | 1 | axi_i2s_adi_0_DMA_REQ_RX_DRLAST
21 | DMA_REQ_RX_DRVALID | O | 1 | axi_i2s_adi_0_DMA_REQ_RX_DRVALID
22 | DMA_REQ_RX_DRTYPE | O | 1 | axi_i2s_adi_0_DMA_REQ_RX_DRTYPE
23 | DMA_REQ_RX_DAREADY | O | 1 | axi_i2s_adi_0_DMA_REQ_RX_DAREADY
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SLOT_WIDTH | 24
C_LRCLK_POL | 0
C_BCLK_POL | 0
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_ADDR_WIDTH | 32
C_BASEADDR | 0x77600000
C_HIGHADDR | 0x7760FFFF
C_FAMILY | virtex6 |  | Name | Value
C_S_AXI_PROTOCOL | AXI4LITE
C_S_AXIS_MM2S_PROTOCOL | XIL_AXI_STREAM_ETH_DATA
C_M_AXIS_S2MM_PROTOCOL | XIL_AXI_STREAM_ETH_DATA
C_DMA_TYPE | 1
C_NUM_CH | 1
C_HAS_TX | 1
C_HAS_RX | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_iic_0 AXI IIC Interface AXI interface to Philips I2C bus v2.1
IP Specs
Core | Version | Documentation
axi_iic | 1.02.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
1 | IIC2INTC_Irpt | O | 1 | axi_iic_0_IIC2INTC_Irpt
2 | Sda_I | I | 1 | util_i2c_mixer_0_upstream_sda_O
3 | Sda_O | O | 1 | axi_iic_0_Sda_O
4 | Sda_T | O | 1 | axi_iic_0_Sda_T
5 | Scl_I | I | 1 | util_i2c_mixer_0_upstream_scl_O
6 | Scl_O | O | 1 | axi_iic_0_Scl_O
7 | Scl_T | O | 1 | axi_iic_0_Scl_T
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_INSTANCE | axi_iic_inst
C_BASEADDR | 0x41620000
C_HIGHADDR | 0x4162FFFF
C_S_AXI_ADDR_WIDTH | 9
C_S_AXI_DATA_WIDTH | 32
C_IIC_FREQ | 100000 |  | Name | Value
C_TEN_BIT_ADR | 0
C_GPO_WIDTH | 1
C_S_AXI_ACLK_FREQ_HZ | 25000000
C_SCL_INERTIAL_DELAY | 0
C_SDA_INERTIAL_DELAY | 0
C_SDA_LEVEL | 1
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_iic_1 AXI IIC Interface AXI interface to Philips I2C bus v2.1
IP Specs
Core | Version | Documentation
axi_iic | 1.02.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
1 | Sda | IO | 1 | axi_iic_1_Sda
2 | Scl | IO | 1 | axi_iic_1_Scl
3 | IIC2INTC_Irpt | O | 1 | axi_iic_1_IIC2INTC_Irpt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_INSTANCE | axi_iic_inst
C_BASEADDR | 0x41600000
C_HIGHADDR | 0x4160FFFF
C_S_AXI_ADDR_WIDTH | 9
C_S_AXI_DATA_WIDTH | 32
C_IIC_FREQ | 100000 |  | Name | Value
C_TEN_BIT_ADR | 0
C_GPO_WIDTH | 1
C_S_AXI_ACLK_FREQ_HZ | 25000000
C_SCL_INERTIAL_DELAY | 0
C_SDA_INERTIAL_DELAY | 0
C_SDA_LEVEL | 1
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_spdif_tx_0 AXI_SPDIF_TX
IP Specs
Core | Version
axi_spdif_tx | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | spdif_tx_o | O | 1 | axi_spdif_tx_0_spdif_tx_o
1 | spdif_data_clk | I | 1 | clock_generator_0_CLKOUT0
2 | DMA_REQ_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
3 | DMA_REQ_RSTN | I | 1 | processing_system7_0_DMA0_RSTN
4 | DMA_REQ_DATYPE | I | 1 | processing_system7_0_DMA0_DATYPE
5 | DMA_REQ_DAVALID | I | 1 | processing_system7_0_DMA0_DAVALID
6 | DMA_REQ_DRREADY | I | 1 | processing_system7_0_DMA0_DRREADY
7 | DMA_REQ_DAREADY | O | 1 | axi_spdif_tx_0_DMA_REQ_DAREADY
8 | DMA_REQ_DRLAST | O | 1 | axi_spdif_tx_0_DMA_REQ_DRLAST
9 | DMA_REQ_DRTYPE | O | 1 | axi_spdif_tx_0_DMA_REQ_DRTYPE
10 | DMA_REQ_DRVALID | O | 1 | axi_spdif_tx_0_DMA_REQ_DRVALID
11 | S_AXI_ACLK | I | 1 | processing_system7_0_FCLK_CLK0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_MIN_SIZE | 0x000001FF
C_BASEADDR | 0x75C00000
C_HIGHADDR | 0x75C0FFFF
C_FAMILY | virtex6
C_S_AXI_PROTOCOL | AXI4LITE
C_S_AXIS_MM2S_PROTOCOL | XIL_AXI_STREAM_ETH_DATA
C_DMA_TYPE | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_vdma_0 AXI Video DMA MemoryMap to/from Stream Video Direct Memory Access for AXI
IP Specs
Core | Version | Documentation
axi_vdma | 5.04.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | m_axis_mm2s_aclk | I | 1 | processing_system7_0_FCLK_CLK1
1 | mm2s_fsync_out | O | 1 | axi_vdma_0_mm2s_fsync_out
2 | mm2s_buffer_almost_empty | O | 1 | axi_vdma_0_mm2s_buffer_almost_empty
3 | mm2s_buffer_empty | O | 1 | axi_vdma_0_mm2s_buffer_empty
4 | mm2s_fsync | I | 1 | axi_hdmi_tx_16b_0_vdma_fs
5 | s_axi_lite_aclk | I | 1 | processing_system7_0_FCLK_CLK0
6 | m_axi_mm2s_aclk | I | 1 | processing_system7_0_FCLK_CLK1
7 | mm2s_introut | O | 1 | axi_vdma_0_mm2s_introut
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
M_AXIS_MM2S | INITIATOR | AXIS | axi_vdma_0_M_AXIS_MM2S | axi_hdmi_tx_16b_0
M_AXI_MM2S | MASTER | AXI | axi_interconnect_2 | processing_system7_0
S_AXI_LITE | SLAVE | AXI | axi_interconnect_1 | 9 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_LITE_ADDR_WIDTH | 9
C_S_AXI_LITE_DATA_WIDTH | 32
C_DLYTMR_RESOLUTION | 125
C_PRMRY_IS_ACLK_ASYNC | 1
C_M_AXI_SG_ADDR_WIDTH | 32
C_M_AXI_SG_DATA_WIDTH | 32
C_NUM_FSTORES | 3
C_USE_FSYNC | 1
C_FLUSH_ON_FSYNC | 1
C_DYNAMIC_RESOLUTION | 1
C_INCLUDE_SG | 0
C_INCLUDE_INTERNAL_GENLOCK | 1
C_ENABLE_VIDPRMTR_READS | 1
C_INCLUDE_MM2S | 1
C_M_AXI_MM2S_DATA_WIDTH | 64
C_M_AXIS_MM2S_TDATA_WIDTH | 64
C_INCLUDE_MM2S_DRE | 0
C_INCLUDE_MM2S_SF | 1
C_MM2S_SOF_ENABLE | 1
C_MM2S_MAX_BURST_LENGTH | 16
C_MM2S_GENLOCK_MODE | 1
C_MM2S_GENLOCK_NUM_MASTERS | 1
C_MM2S_GENLOCK_REPEAT_EN | 0
C_MM2S_LINEBUFFER_DEPTH | 128
C_MM2S_LINEBUFFER_THRESH | 8
C_M_AXI_MM2S_ADDR_WIDTH | 32
C_M_AXIS_MM2S_TUSER_BITS | 1
C_INCLUDE_S2MM | 0
C_M_AXI_S2MM_DATA_WIDTH | 32
C_S_AXIS_S2MM_TDATA_WIDTH | 32
C_INCLUDE_S2MM_DRE | 0
C_INCLUDE_S2MM_SF | 1
C_S2MM_SOF_ENABLE | 1
C_S2MM_MAX_BURST_LENGTH | 16
C_S2MM_GENLOCK_MODE | 0
C_S2MM_GENLOCK_NUM_MASTERS | 1 |  | Name | Value
C_S2MM_GENLOCK_REPEAT_EN | 1
C_S2MM_LINEBUFFER_DEPTH | 128
C_S2MM_LINEBUFFER_THRESH | 4
C_M_AXI_S2MM_ADDR_WIDTH | 32
C_S_AXIS_S2MM_TUSER_BITS | 1
C_FAMILY | virtex6
C_INSTANCE | axi_vdma
C_BASEADDR | 0x43000000
C_HIGHADDR | 0x4300FFFF
C_S_AXI_LITE_PROTOCOL | AXI4LITE
C_S_AXI_LITE_SUPPORTS_READ | 1
C_S_AXI_LITE_SUPPORTS_WRITE | 1
C_M_AXI_SG_PROTOCOL | AXI4
C_M_AXI_SG_SUPPORTS_THREADS | 0
C_M_AXI_SG_THREAD_ID_WIDTH | 1
C_M_AXI_SG_SUPPORTS_NARROW_BURST | 0
C_M_AXI_SG_SUPPORTS_READ | 1
C_M_AXI_SG_SUPPORTS_WRITE | 0
C_M_AXI_MM2S_PROTOCOL | AXI4
C_M_AXI_MM2S_SUPPORTS_THREADS | 0
C_M_AXI_MM2S_THREAD_ID_WIDTH | 1
C_M_AXI_MM2S_SUPPORTS_NARROW_BURST | 0
C_M_AXI_MM2S_SUPPORTS_READ | 1
C_M_AXI_MM2S_SUPPORTS_WRITE | 0
C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH | 0
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING | 4
C_M_AXI_S2MM_PROTOCOL | AXI4
C_M_AXI_S2MM_SUPPORTS_THREADS | 0
C_M_AXI_S2MM_THREAD_ID_WIDTH | 1
C_M_AXI_S2MM_SUPPORTS_NARROW_BURST | 0
C_M_AXI_S2MM_SUPPORTS_WRITE | 1
C_M_AXI_S2MM_SUPPORTS_READ | 0
C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH | 0
C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING | 4
C_M_AXIS_MM2S_PROTOCOL | XIL_AXI_STREAM_VID_DATA
C_S_AXIS_S2MM_PROTOCOL | XIL_AXI_STREAM_VID_DATA Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
IP | TOC
clock_generator_0 Clock Generator Clock generator for processor system.
IP Specs
Core | Version | Documentation
clock_generator | 4.03.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | RST | I | 1 | net_gnd
1 | CLKOUT0 | O | 1 | clock_generator_0_CLKOUT0
2 | CLKIN | I | 1 | processing_system7_0_FCLK_CLK2
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_DEVICE | NOT_SET
C_PACKAGE | NOT_SET
C_SPEEDGRADE | NOT_SET
C_CLKIN_FREQ | 200000000
C_CLKOUT0_FREQ | 12288135
C_CLKOUT0_PHASE | 0
C_CLKOUT0_GROUP | NONE
C_CLKOUT0_BUF | TRUE
C_CLKOUT0_VARIABLE_PHASE | FALSE
C_CLKOUT1_FREQ | 0
C_CLKOUT1_PHASE | 0
C_CLKOUT1_GROUP | NONE
C_CLKOUT1_BUF | TRUE
C_CLKOUT1_VARIABLE_PHASE | FALSE
C_CLKOUT2_FREQ | 0
C_CLKOUT2_PHASE | 0
C_CLKOUT2_GROUP | NONE
C_CLKOUT2_BUF | TRUE
C_CLKOUT2_VARIABLE_PHASE | FALSE
C_CLKOUT3_FREQ | 0
C_CLKOUT3_PHASE | 0
C_CLKOUT3_GROUP | NONE
C_CLKOUT3_BUF | TRUE
C_CLKOUT3_VARIABLE_PHASE | FALSE
C_CLKOUT4_FREQ | 0
C_CLKOUT4_PHASE | 0
C_CLKOUT4_GROUP | NONE
C_CLKOUT4_BUF | TRUE
C_CLKOUT4_VARIABLE_PHASE | FALSE
C_CLKOUT5_FREQ | 0
C_CLKOUT5_PHASE | 0
C_CLKOUT5_GROUP | NONE
C_CLKOUT5_BUF | TRUE
C_CLKOUT5_VARIABLE_PHASE | FALSE
C_CLKOUT6_FREQ | 0
C_CLKOUT6_PHASE | 0
C_CLKOUT6_GROUP | NONE
C_CLKOUT6_BUF | TRUE
C_CLKOUT6_VARIABLE_PHASE | FALSE
C_CLKOUT7_FREQ | 0
C_CLKOUT7_PHASE | 0
C_CLKOUT7_GROUP | NONE
C_CLKOUT7_BUF | TRUE
C_CLKOUT7_VARIABLE_PHASE | FALSE
C_CLKOUT8_FREQ | 0
C_CLKOUT8_PHASE | 0
C_CLKOUT8_GROUP | NONE
C_CLKOUT8_BUF | TRUE
C_CLKOUT8_VARIABLE_PHASE | FALSE
C_CLKOUT9_FREQ | 0
C_CLKOUT9_PHASE | 0
C_CLKOUT9_GROUP | NONE
C_CLKOUT9_BUF | TRUE
C_CLKOUT9_VARIABLE_PHASE | FALSE
C_CLKOUT10_FREQ | 0 |  | Name | Value
C_CLKOUT10_PHASE | 0
C_CLKOUT10_GROUP | NONE
C_CLKOUT10_BUF | TRUE
C_CLKOUT10_VARIABLE_PHASE | FALSE
C_CLKOUT11_FREQ | 0
C_CLKOUT11_PHASE | 0
C_CLKOUT11_GROUP | NONE
C_CLKOUT11_BUF | TRUE
C_CLKOUT11_VARIABLE_PHASE | FALSE
C_CLKOUT12_FREQ | 0
C_CLKOUT12_PHASE | 0
C_CLKOUT12_GROUP | NONE
C_CLKOUT12_BUF | TRUE
C_CLKOUT12_VARIABLE_PHASE | FALSE
C_CLKOUT13_FREQ | 0
C_CLKOUT13_PHASE | 0
C_CLKOUT13_GROUP | NONE
C_CLKOUT13_BUF | TRUE
C_CLKOUT13_VARIABLE_PHASE | FALSE
C_CLKOUT14_FREQ | 0
C_CLKOUT14_PHASE | 0
C_CLKOUT14_GROUP | NONE
C_CLKOUT14_BUF | TRUE
C_CLKOUT14_VARIABLE_PHASE | FALSE
C_CLKOUT15_FREQ | 0
C_CLKOUT15_PHASE | 0
C_CLKOUT15_GROUP | NONE
C_CLKOUT15_BUF | TRUE
C_CLKOUT15_VARIABLE_PHASE | FALSE
C_CLKFBIN_FREQ | 0
C_CLKFBIN_DESKEW | NONE
C_CLKFBOUT_FREQ | 0
C_CLKFBOUT_PHASE | 0
C_CLKFBOUT_GROUP | NONE
C_CLKFBOUT_BUF | TRUE
C_PSDONE_GROUP | NONE
C_EXT_RESET_HIGH | 1
C_CLK_PRIMITIVE_FEEDBACK_BUF | FALSE
C_CLKOUT0_DUTY_CYCLE | 0.500000
C_CLKOUT1_DUTY_CYCLE | 0.500000
C_CLKOUT2_DUTY_CYCLE | 0.500000
C_CLKOUT3_DUTY_CYCLE | 0.500000
C_CLKOUT4_DUTY_CYCLE | 0.500000
C_CLKOUT5_DUTY_CYCLE | 0.500000
C_CLKOUT6_DUTY_CYCLE | 0.500000
C_CLKOUT7_DUTY_CYCLE | 0.500000
C_CLKOUT8_DUTY_CYCLE | 0.500000
C_CLKOUT9_DUTY_CYCLE | 0.500000
C_CLKOUT10_DUTY_CYCLE | 0.500000
C_CLKOUT11_DUTY_CYCLE | 0.500000
C_CLKOUT12_DUTY_CYCLE | 0.500000
C_CLKOUT13_DUTY_CYCLE | 0.500000
C_CLKOUT14_DUTY_CYCLE | 0.500000
C_CLKOUT15_DUTY_CYCLE | 0.500000
C_CLK_GEN | UPDATE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
util_i2c_mixer_0 UTIL_I2C_MIXER
IP Specs
Core | Version
util_i2c_mixer | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | upstream_sda_O | O | 1 | util_i2c_mixer_0_upstream_sda_O
1 | upstream_sda_I | I | 1 | axi_iic_0_Sda_O
2 | upstream_sda_T | I | 1 | axi_iic_0_Sda_T
3 | upstream_scl_O | O | 1 | util_i2c_mixer_0_upstream_scl_O
4 | upstream_scl_I | I | 1 | axi_iic_0_Scl_O
5 | upstream_scl_T | I | 1 | axi_iic_0_Scl_T
6 | downstream_scl | IO | 1 | util_i2c_mixer_0_downstream_scl
7 | downstream_sda | IO | 1 | util_i2c_mixer_0_downstream_sda
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_WIDTH | 2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
util_vector_logic_0 Utility Vector Logic 'Simple logic functions, and, or, xor, not.'
IP Specs
Core | Version | Documentation
util_vector_logic | 1.00.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | Res | O | 1 | util_vector_logic_0_Res
1 | Op1 | I | 1 | net_otg_oc
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_OPERATION | not
C_SIZE | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Timing Information | TOC Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.